Pipelined error detection and correction apparatus with programmable address trap

ABSTRACT

An error detection and correction apparatus utilizing seven internally generated check bits which are applied to incoming data signals on the next clock. The combination data signals are written into the system random access memory and are reapplied to the error detection and correction apparatus. An address trap register is programmed to trap the address of the single or multiple bit errors. The address trap register also captures the error flags and the syndrome bit so that detected faults can be isolated. A single bit error correction circuit is utilized to correct single bit errors in the data signal.

STATEMENT OF GOVERNMENT INTEREST

The invention described herein may be manufactured and used by or forthe Government for governmental purposes without the payment of anyroyalty thereon.

BACKGROUND OF THE INVENTION

The present invention relates broadly to an error detection apparatus,and in particular to a pipelined error detection and correctionapparatus utilizing a programmable address trap.

It is well known that the reliability of data stored in memory devicescan be significantly increased through the use of error detection andcorrection (EDC) techniques. Typically, the devices to implement thesetechniques can detect and flag all single, double, and some more thantwo bit errors. Single bit errors (within a word) can also be corrected.These error detection and correction techniques can be used not only forfault detection but also for fault isolation. In order to isolate afault to the memory chip level, it is necessary to know not only that anerror has occurred but also whether it was a single or multiple biterror and at what memory address it occurred. However, the addition oferror detection and correction circuits create and/or present thefollowing problems:

A. Loading - The addition of error detection and correction devicesincreases the load on the output of the memory devices and therefore thedevice access time. This problem is typically solved by adding bufferdevices. This invention solves the problem by adding a separate inputport for the memory devices which presents a minimum load withoutincreasing the component count.

B. Speed - Newer and faster memory devices require faster errordetection and correction devices. Currently available error detectionand correction devices were designed for applications where they aretightly coupled to the central processing unit (CPU) and therefore donot take advantage of speed enhancements permitted by a pipelined errordetection and correction device. This invention makes use of clockedinput and output pipelined registers and can perform a correction inapproximately 25 nanoseconds (typical at 25 degrees C.). This can beachieved by using VHSIC CMOS technology. At this speed all data can beclocked through the error detection and correction device pipelineregisters and the data flow is not interrupted to perform an errorcorrection operation.

C. Fault Isolation - Fault isolation can be simple in a memory that istightly coupled to a central processing unit, but can be difficult whenthe memory array is being accessed over a system bus which interfacesthe memory array to the central processing unit through two businterface units. In such a case, the central processing unit does notknow the memory address of the error. This invention solves the problemby having programmable error flag, check bit, and address traps whichthe central processing unit can read via the data port.

D. Testing - Adding an error detection and correction device to thememory system now requires a test method to validate the properoperation of the error detection and correction device. Some currenterror detection and correction devices have diagnostic modes but theirability to provide fault isolation features is limited. This inventionincorporates the typical diagnostic features but also has data pathsthat permit wrap tests of the address and check bits.

E. Device Count - Additional devices need to be added in order to solvemost of the above problems. This in turn causes more problems. Thisinvention provides a monolithic solution to all the above problems.

The state of the art of error detection and correction apparatus arewell represented and alleviated to some degree by the prior artapparatus and approaches which are contained in the following U.S.patents:

U.S. Pat. No. 3,644,902 issued to Beausoleil on Feb. 22, 1972;

U.S. Pat. No. 4,335,459 issued to Miller on June 15, 1982; and

U.S. Pat. No. 4,488,298 issued to Bond et al on Dec. 11, 1984.

U.S. Pat. No. 3,644,902, Beausoleil, discloses a memory having circuitsfor correcting single errors in a word read from the memory with meansto reconfigure the memory so that a configuration having a double,uncorrectable, error is changed to a configuration having two single,correctable errors.

U.S. Pat. No. 4,335,459, Miller, discusses the production yield andreliability of random access integrated circuit memory chips which aregreatly increased by providing a memory capacity greater than thenominal capacity of the chip and providing error correction circuitry onthe chip.

U.S. Pat. No. 4,488,298, Bond et al, relates to a fault alignmentexclusion method and apparatus which operates to prevent the alignmentof two or more defective bit storage locations at an address in a memoryarray. The present invention is directed to an error detection andcorrection apparatus which is intended to satisfy the above-mentionedprior art problems.

SUMMARY OF THE INVENTION

The present invention utilizes a pipelined error detection andcorrection circuit with programmable address trap and is a monolithic,solid state, gate array personalization design for use in memory systemsto provide fault tolerance, fault isolation, and diagnostic features. Itprovides the ability to detect all single and double bit errors in a 32bit data word. It also detects some three or more bit errors in a 32 bitdata word. All single bit errors can be corrected; all double bit errorswill be flagged but not corrected; and some three or more bit errorswill be flagged. Data is pipelined through the device from an input portand register to an output register and port. Therefore all operationsare performed within one clock period. There is a built-in trap whichcan be programmed to trap the address of the first single or multiplebit error. This trap also captures the error flags and the syndrome bitsso that detected faults can be isolated. The contents of the trap can beread out of the data output port.

It is one object of the present invention, therefore, to provide animproved error detection and correction apparatus.

It is another object of the present invention to provide an improvederror detection and correction apparatus which uses a separate inputport for the memory devices and presents a minimum load withoutincreasing the component count.

It is yet another object of the present invention to provide an improvederror detection and correction apparatus which utilizes clocked inputand output pipelined registers and can perform a correction inapproximately 25 nanoseconds.

It is still a further object of the present invention to provide animproved error detection and correction apparatus wherein all data canbe clocked through the pipeline registers and the data flow is notinterrupted to perform an error correction operation.

It is a further object of the present invention to provide an improvederror detection and correction apparatus having programmable error flag,check bit, and address traps which the central processing unit can readvia the data output port.

It is yet another object of the present invention to provide an improvederror detection and correction apparatus which incorporates the typicaldiagnostic features and also has data paths that permit wrap test of theaddress and check bits.

These and other advantages, objects and features of the invention willbecome more apparent after considering the following description takenin conjunction with the illustrative embodiment in the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a and 1b are a block diagram of the error detection andcorrection apparatus according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Turning now to FIG. 1, there is shown a block diagram of the errordetection and correction apparatus, the error detection and correctiongate array (GA) has the following functional elements. The mode register10 is loaded by the clock signal, CLK 02 and holds the error detectionand correction gate array mode such as, Generate, Detect/Correct,Diagnostic, etc. The control logic register 12 decodes the mode linesfor mode and diagnostic information to control the data in and data outmultiplexers 14, 16, and to enable or inhibit certain features.

The data input multiplexer unit 14 selects between two 32 bit data inputports depending on the gate array mode. One input port is from the arrayof memory devices and provides a minimum load to the memory devices. Theother data input port is for the source data when the memory is in the"write" mode. The data input register unit 18 is a 32 bit register thatholds the input data while parity bits are being generated. The checkbit register unit 20 holds the check bits from the selected randomaccess memory (SRAM) while the gate array logic checks for errors in thedata. The check bit parity trees unit 22 generate the parity bits neededbased on the truth table for a modified Hamming (39, 32) code (see TableI).

The syndrome generator logic input multiplexer unit 24 (SGLI mux)outputs zeros in the generate mode, outputs the check bits in thedetect/correct mode, or diagnostic check bits in certain diagnosticmodes. The syndrome generator logic unit 26 is a set of seven (7)exclusive nor gates which operate on the output of the check bit paritytrees and the output of the syndrome generator logic input multiplexer.

                                      TABLE I                                     __________________________________________________________________________    MODIFIED HAMMING (39, 32) CODE USED FOR THE                                   ERROR DETECTION AND CORRECTION APPARATUS                                      __________________________________________________________________________    CHECK WORD                                                                             32-BIT DATA WORD                                                     BIT      31                                                                              30                                                                              29                                                                              28                                                                              27                                                                              26                                                                              25                                                                              24                                                                              23                                                                              22                                                                              21                                                                              20                                                                              19                                                                              18                                                                              17                                                                              16                                     __________________________________________________________________________    CS0      X   X X   X         X   X X X                                        CS1            X   X   X   X   X   X X                                        CS2      X   X     X X   X     X X     X                                      CS3          X X X       X X X       X X                                      CS4      X X             X X X X X X                                          CS5      X X X X X X X X                                                      CS6      X X X X X X X X                                                      __________________________________________________________________________    CHECK WORD                                                                             32-BIT DATA WORD                                                     BIT      15                                                                              14                                                                              13                                                                              12                                                                              11                                                                              10                                                                              09                                                                              08                                                                              07                                                                              06                                                                              05                                                                              04                                                                              03                                                                              02                                                                              01                                                                              00                                     __________________________________________________________________________    CS0        X     X   X X X X   X       X                                      CS1            X   X   X   X   X   X X X                                      CS2      X   X     X X   X     X X     X                                      CS3          X X X       X X X       X X                                      CS4      X X             X X X X X X                                          CS5      X X X X X X X X                                                      CS6                      X X X X X X X X                                      __________________________________________________________________________     The seven checks bits (CS0 through CS6) are parity bits derived from the      matrix of data bits as indicated by "X" for each bit.                    

The correction gate unit 28 is a set of seven NAND gates which outputall ones in the generate modes and the syndrome bits inverted in thedetect/correct modes. The bit in-error decode logic unit 30 receives theseven bits from the correction gate and decodes them for single biterrors. If there is a single bit error then one of the 32 outputs willbe a zero. If there is not a single bit error then all 32 outputs willbe ones.

The single bit error unit 32 correction logic receives the 32 bits ofdata from the data input register and the 32 bits from the bit-in-errordecode logic. If there is a single bit error then one of the 32 bitsfrom the bit-in-error decode logic will be a zero. The single bit errorcorrection logic will invert that bit in the data from the data inputregister thereby correcting it. Data that is error free or that has morethan one error is passed with no correction.

The data output multiplexer unit 16 is a thirty two bit 2 to 1multiplexer that selects between the output of the single bit errorcorrection logic and address trap register. The data output registerunit 34 is a thirty two bit register that holds the data from the dataoutput multiplexer.

The syndrome check multiplexer unit 36 is a seven bit 3 to 1 multiplexerthat selects between inputs from the check bit register, inputs from thesyndrome generator logic, or inputs from the diagnostic register.

The syndrome/check bit output register unit 38 is a seven bit registerthat receives seven bits from the syndrome check multiplexer and outputsthem from the error detection and correction gate array.

The error detector unit 40 decodes the output of the syndrome generatorlogic to determine whether no error, a single bit error, a double biterror, or more than a double bit error has occurred. The error outputregister unit 42 receives inputs from the error detector and outputsthem from the error detection and correction gate array.

The diagnostic register unit 44 is an eighteen bit register that isloaded from the data input port under control of the LEDIAG signal. Bits0 through 6 provide the diagnostic check bits. Bits 7 through 14 provideerror detection and correction control signals. Bits 15 through 17control the address trap.

The address trap register unit 46 is a multiple level register that isdesigned to trap the address at which an error occurs. It outputs thirtytwo bits to the data output multiplexer. Bits 0 through 21 contain theaddress data. Bit 22 is always zero. Bits 23 through 29 are the outputof the syndrome check multiplexer at the time of the trapped error. Bits30 and 31 are the output of the error detector at the time of thetrapped error.

The clock distribution unit 48 logic provides the buffering and drivefor the clock signal to all of the error detection and correction gatearray registers. The built-in test controller unit 50 is standard on allVHSIC gate arrays. It provides a means for a built-in test of the errordetection and correction gate array. The built-in test controller may beused to verify operation of the error detection and correction gatearray at any test level from wafer test to module or system level testwhere it may be used to fault isolate down to the component i.e., gatearray level.

Operating and Diagnostic Modes

1. EDC Generate Mode

When data is being written into the RAMs the error detection andcorrection gate arrays is put in the generate mode. The data is receivedas thirty two bit words. These words are clocked into the errordetection and correction gate array where seven check bits aregenerated. On the next clock the thirty two data bits and seven checkbits are output from the EDC gate array. These thirty nine bits are thenwritten into the selected RAMs. The seven check bits are generated byusing a modified Hamming 39/32 code. The particular code was selecteddue to its ability to detect and correct all single bit errors and todetect all double bit errors. This code also detects some errorcombinations of three or more bits.

2. EDC Detect/Correct Mode

When data is being read from the RAMs, the error detection andcorrection gate array is put into the Detect/Correct mode. In this modeit receives thirty nine bits of data from the RAM array. This data isclocked into the thirty two bit data input register and the seven bitcheck bit register. There are two discrete outputs from the errordetection and correction gate array which are enabled in this mode. Theyare an error flag (ERROR) and a multiple bit error flat (MERROR). Theyflag the following conditions:

    ______________________________________                                        ERROR*   MERROR*    Condition                                                 ______________________________________                                        HIGH     HIGH       No error detected                                         LOW      HIGH       Single bit error detected/corrected                       LOW      LOW        Multiple bit error detected                               ______________________________________                                         Note:                                                                         The "*" = an active low signal                                           

3. EDC Diagnostic Modes

The error detection and correction gate array has diagnostic modes whichallow it to be programmed and tested when it is in an operating module.The following modes are available:

(a) Diagnostic Generate

(b) Diagnostic Detect/Correct

(c) Diagnostic Detect/Correct with ERROR flags inhibited

(d) Diagnostic Pass

(e) Reset Address Trap

(f) Set Address Trap for single bit errors

(g) Set Address Trap for multiple bit errors

(h) Set Address Trap for any errors

(i) Read Address Trap

(j) Special Diagnostic modes which allow the BMM to control the EDC gatearray data paths

Experimental Results - The RTL model of the EDC gate array has beenverified by exercising it at the gate array level. The test vectors usedverified its ability to generate check bits in the "Write" mode and todetect and correct single bit errors in the "Read" mode. The ability topass error free data and to detect all two bit errors was also verifiedas was the address trap feature.

Equivalents and alternatives - The error detection and correction gatearray could be implemented in technologies other than the VHSIC CMOSwhich was presented here. However, non-VHSIC technologies would probablybe slower although this may be acceptable in some applications. Thechoice of a 5 volt device rather than a 3.3 volt device may be preferredin some applications. The total gate count for the described design was2588 including the BIT controller which requires 621 gate sites. Othertechniques for providing built-in test could be implemented withoutaffecting the basic error detection and correction operational anddiagnostic modes. Other monolithic alternatives would have to be able toprovide the required number of I/0 pins and have the necessary number ofavailable gate sites. Non monolithic alternatives will significantlyincrease the device count, be slower, dissipate more power, be lessreliable, and not be able to provide the diagnostic features.

Although the invention has been described with reference to a particularembodiment, it will be understood to those skilled in the art that theinvention is capable of a variety of alternative embodiments within thespirit and scope of the appended claims.

What is claimed is:
 1. An error detection and correction apparatus withprogrammable address trap comprising in combination:means for receivingand holding data signals, said data means receiving data signals from arandom access memory, means for generating check bits, said check bitmeans generating a predetermined number of check bits, said check bitsare parity bits which are derived from said data signals, means foroutputting signals, said signal output means operatively connected tosaid data means and said check bit means to receive said data signalsand said check bits therefrom, said signal output means applying saiddata signals and check bits to said random access memory, said randomaccess memory applying said data signals and check bits to said datameans, means for error correction, said error correction means receivingsaid check bits and said data signals from said data means, said errorcorrection means decodes said check bits for signal bit errors, saiderror correction means will correct a single bit error in said datasignals by inverting the error bit in said data signals, said datasignals either error free or error corrected, is passed to said signaloutput means, said error correction means provides an error signal, saiderror signal is coded to represent either no error, a single bit error,a double bit error, or more than a double bit error, an address trapregister operatively connected to said signal output means to trap theaddress of said data signal at which an error occurs, and, means forerror detection, said error detection means operatively connected tosaid error correcting means to receive said error signal therefrom, saiderror detection means decoding said error signal to determine the errorstate.
 2. An error detection and correction apparatus as described inclaim 1 wherein said data means comprises in combination:a data-inmultiplexer to alternatively receive said data signals at a first portand said data signals and check bits at a second port, and, a data-inregister to receive and hold said data bits from said data-inmultiplexer.
 3. An error detection and correction apparatus as definedin claim 1 wherein said predetermined number of check bits compriseseven bits.
 4. An error detection and correction apparatus as defined inclaim 1 wherein said signal output means comprises in combination:adata-out multiplexer is operatively connected to said error correctionmeans and said address trap register to select the output from either,and, a data-out register operatively connected to said data-outmultiplexer to receive data signals therefrom.
 5. An error detection andcorrection apparatus as defined in claim 1 wherein said error correctionmeans comprises in combination:a correction gate to correct said datasignals, a bit-in error decode logic operatively connected to saidcorrection gate to decode the signal therefrom for single bit errors,said bit-in error decode logic providing an error correction signal, anda single bit error correction logic operatively connected to said datameans and said bit-in-error decode logic to correct said data signals asdirected by said error correction signal.